The present invention relates generally to semiconductor device manufacture and, particularly, to improvements in plasma planarization of semiconductor device layers and the formation of interlevel interconnect locations. More particularly, the present invention relates to a method for simultaneously altering the underlying topography and the formation of interlevel interconnect apertures having an improved profile to facilitate reliable metal adherence and coverage to thereby improve device yields.
As integrated circuit geometries increase in complexity and decrease in dimensions it becomes increasingly important to provide component layers with smooth or planar surface topographies. Planar surfaces are important in MOS technologies where initial layer topographies are often extremely rough. For example, where a metallic or conductive path is applied to a semiconductor substrate, the sidewalls and edges of that path typically present substantial steps which may be unacceptable for certain subsequent processing. For instance, these steps would often inhibit proper application of additional device layers. Also, in the fabrication of multilevel devices it is generally necessary to form apertures through one device layer to an underlying layer. The sidewall height and angle of these apertures is often too abrupt for good metal coverage.
To reduce sidewall angles and soften edges, previous fabrication processes have included high temperature "reflow" techniques. The substrate and glass thereon would be heated to temperatures where the glass softens and starts to melt. The substrate, however, maintains its stability at these temperatures. Unfortunately, reflow techniques have often proved unsatisfactory where metal is used. To insulate these paths, oxide layers are typically applied between them. These oxide layers substantially conform to the underlying surface topography. Thus, subsequent paths applied directly to the oxide would not have a planar base surface. Without a planar base surface, designing complex, multi-layer circuits become extremely difficult. Attempts to apply reflow techniques to the oxide layers are not successful. Temperatures high enough to soften the oxide and cause it to flow into and fill surface steps also cause underlying metal paths to melt or peel off adjacent layers or alloy with the silicon. This results in silicon surface pits and resultant device failures. Further, such high temperature processing will generally enlarge device dimensions and promote poor features size control which subsequently causes loss of device packing density.
Recently, low temperature plasma etching techniques for smoothing rough and irregular surface topographies have been developed. These are often referred to as "plasma planarization" or "plasma filing". As seen in the sectional view of FIG. 1, plasma planarization typically involves the use of a sacrificial layer 10 which is applied over rough topography 20 of insulating layer 30. Rough topography 20 may, for example, result from conformity of insulating layer 30 to metal path 40 formed on insulative layer 50 of substrate base 60. Prior research and experimentation have been directed toward achieving a planar surface shown by dashed line 15 on sacrificial layer 10. This multi-layered product is subjected to plasma etching in a gas environment to completely or partially remove sacrificial layer 10 and portions of insulating layer 30. Sacrificial layer 10 is etched away at the same rate as the material of insulating layer 30. As a result, the topography of relatively smooth surface 15 can be replicated on the surface of insulating layer 30 without detrimentally effecting metal path 40.
Such plasma planarization techniques have been used to smooth surfaces of several materials, including polysilicon, nitrides, and various glasses. A variety of sacrificial layers have also been used, including photoresists, polyimide, and nitrides. Unfortunately, while previous plasma planarization techniques may be suitable for fabrication of some larger, less detailed integrated circuits, they do not produce surfaces which are sufficiently planar for many smaller and more complex circuit devices.
Further difficulties also arise with the relatively narrow processing constraints of these prior techniques. According to these prior techniques, the ratio of the etch rates of the sacrificial layer to the underlying insulating layer must, as nearly as possible, be unity if the topography of surface 15 is to be properly replicated. Even the smallest deviation from a unity ratio is considered undesirable.
A solution of the above difficulties has been described in copending U.S. Ser. No. 591,597 entitled "Plasma Sculpturing With A Non-Planar Sacrificial Layer" and owned by the assignee of the present invention now U.S. Pat. No. 4,515,652. The above patent describes a method of plasma planarization of the surface topography of a substrate layer wherein a sacrificial layer, having an etch rate substantially different from the etch rate of the substrate layer, is applied to the surface topography of that substrate layer. The sacrificial layer 10 and substrate layer 30 are then plasma etched to remove the sacrificial layer 10 and portions of the substrate layer 30. The ratio of substrate to sacrificial layer etch rate can be controlled to compensate for non-planar surface features of the sacrificial layer such that the resulting substrate surface topography is planar. Control of this etch rate ratio is accomplished by selecting appropriate materials forming the sacrificial layer for a given plasma environment and by selecting the appropriate plasma environment for a given material forming the sacrificial layer. This process is a "low temperature" process which is suitable for multilayer devices which may have previously applied metal contacts or lines that could be damaged by temperatures high enough to cause the surface layers to melt or flow.
The present invention relates to an improved method of fabricating semiconductor devices, and more particularly to the fabrication of devices incorporating multilevel interconnect technology.
A desirable process for the fabrication of multilevel interconnect semiconductor devices would provide smoothing of the interlevel dielectric, etching of apertures which will be used for interlevel connections and tapering of the apertures to improve interconnect step coverage into the apertures without requiring high temperatures. The most common method of tapering the apertures is to depend on the taper of the aperatures in the photoresist being transferred to the oxide during the erosion of the photo resist. This method of tapering the photoresist is not easily controlled thus it is difficult to obtain uniformity in the manufactured end products. Gwozdz, U.S. Pat. No. 4,451,326 issued May 29, 1984 is illustrative of the attempts being made to provide an improved aperture profile for facilitating good metal coverage in the aperture. The multi-step process described by Gwozdz is cumbersome and only serves to reduce the step height into the aperture.
Another approach to improving planarization has relied on the melting of the aperture sidewalls causing the apertures to taper, thus improving metal adherence. However, such techniques have not provided reliable device integrity. A description of this technique is provided by Kern and Rosier, "Advances in Deposition Processes for Passivation Films" J. Vac. Sci. Technical, Vol. 14, No. 5, Sept./Oct. 1977.
It is an object of the present invention to provide a tapered profile to an oxide aperture while simultaneously utilizing the sculpturing technology described herein.
It is a further object of the present invention to simultaneously provide a tapered aperture and a sculptured underlying topography without requiring any increase in the number of process steps beyond those ordinarily required for forming a photoresist opening and aperture etch.